1. Field of the Invention
The present invention relates to the field of data processing. More particularly, the present invention relates to prefetching data for a processor by means of an address list.
2. Description of the Related Art
Efficient memory management is crucial for allowing a processor to realize its full potential to process data efficiently. Memory management includes dynamically determining data that is required by a processor in future processing steps. The data is fetched in advance into a data cache of the processor (“prefetching”). Several prefetching methods exist having been developed to increase the efficiency of memory management. For example, there exist history based prediction strategies analyzing a history of unsuccessful access trials for predicting which data shall be prefetched.
Processing systems making use of cache memory are disclosed in the prior art. Cache memories are very high-speed memory devices increasing the speed of the processor by making prefetched data available to the processor with a minimum amount of latency. Although cache memory is only a small fraction of the size of the main memory, typically a large fraction of memory requests are successfully found in the fast cache memory, because of the “locality of reference” property of programs. This means that memory references used by a programmer during a given time interval tend to be confined to a few localized areas of memory.
When a processor is to retrieve some required data from the main memory, at first the cache is examined. If the required data is already found in the cache (because it was prefetched), the data is read from the (fast) cache. The (comparatively slow) main memory is not accessed. Only in case the required data is not found in the cache, the main memory is accessed.
Thus, ideally, all required data are prefetched far enough in advance so that a copy of the data is already in the fast cache when the processor needs it. The amount of data that can actually be prefetched is, however, limited by the small size of the fast cache memory.